RT Journal Article
JF Parallel Algorithms / Architecture Synthesis, AIZU International Symposium on
YR 1997
VO 00
IS
SP 74
TI Instruction-level parallel processors-dynamic and static scheduling tradeoffs
A1 M.J. Flynn,
A1 K.W. Rudd,
K1 parallel architectures; instruction level parallel processors; static scheduling tradeoffs; high performance computer architecture; dynamic scheduling techniques; multiple operations; low complexity designs; high complexity designs; real systems
AB Recently, high performance computer architecture has focused on dynamic scheduling techniques to issue and execute multiple operations concurrently. These designs are complex and have frequently shown disappointing performance. A complementary approach is the use of static scheduling techniques to exploit the same parallelism. We describe some of the tradeoffs between the use of static and dynamic scheduling techniques and show that with appropriate scheduling, low complexity designs using only static scheduling have significant advantages over high complexity designs using dynamic scheduling in real systems.
PB IEEE Computer Society, [URL:http://www.computer.org]
SN
LA English
DO 10.1109/AISPAS.1997.581630
LK http://doi.ieeecomputersociety.org/10.1109/AISPAS.1997.581630