RT Journal Article
JF Parallel Algorithms / Architecture Synthesis, AIZU International Symposium on
YR 1997
VO 00
IS
SP 66
TI Memory Hierarchy Design for Jetpipeline: To Execute Scalar and Vector Instructions in Parallel
A1 Takehito Sasaki,
K1
AB Superscalar and VLIW architectures are based on instruction-level parallelism (ILP), which ideally achieve high performance to execute multiple instructions in parallel. However, the system performance is restricted because of the Von Neumann bottleneck. Therefore, the memory hierarchy design is very important in this kind of architectures.
PB IEEE Computer Society, [URL:http://www.computer.org]
SN
LA English
DO 10.1109/AISPAS.1997.581628
LK http://doi.ieeecomputersociety.org/10.1109/AISPAS.1997.581628