RT Journal Article
JF Parallel Algorithms / Architecture Synthesis, AIZU International Symposium on
YR 1997
VO 00
IS
SP 58
TI Design of High-Performance Massively Parallel Architectures Under Pin Limitations and Non-Uniform Propagation Delay
A1 Chi-Hsiang Yeh,
A1 Behrooz Parhami,
K1
AB Inter-module bandwidth is one of the major constraints on the performance of current and future parallel systems. In this paper, we propose and evaluate several high-performance bus-based parallel architectures, including bus-based cyclic networks (BCNs) and quotient cyclic networks (BQCNs), which are particularly efficient in view of their respective inter-module communication patterns. The inter-cluster connection in a BCN is defined on a set of nodes whose addresses are cyclic shifts of one another. The node degree of a basic BCN is 3; while those of BQCNs and enhanced BCNs can vary from a small constant (e.g., 2) to as large as required, thus providing flexibility and effective tradeoff between cost and performance. A variety of algorithms can be performed efficiently on these networks, thus proving the versatility of BCNs and BQCNs.
PB IEEE Computer Society, [URL:http://www.computer.org]
SN
LA English
DO 10.1109/AISPAS.1997.581626
LK http://doi.ieeecomputersociety.org/10.1109/AISPAS.1997.581626