RT Journal Article
JF Parallel Algorithms / Architecture Synthesis, AIZU International Symposium on
TI An Architecture based on the Memory Mapped Node Addressing in Reconfigurable Interconnection Network
A1 T. Ikedo,
AB This paper proposes a new architecture for a scalable supercomputing machine, based on a distributed virtual shared memory system. The processing elements used in this system consist of an ASIC embedding 5 PE, 20 floating point multipliers, 15 adders, and one divider and square root arithmetic unit in a single chip. The 5 PE are interconnected with a complete graph. The reconfigurable architecture is designed for dynamic high-performance applications like virtual reality or multimedia systems. One chip implements a cluster, and an inter-cluster network can be established through a multiple interconnection network of these chips. It has 3.0~Gflops/chip as hardware peak performance, and can be scaled by an optical link via a specified router.
PB IEEE Computer Society, [URL:http://www.computer.org]