RT Journal Article
JF Electronic Design, Test and Applications, IEEE International Workshop on
YR 2006
VO 00
SP 414
TI Modified Montgomery Modular Multiplication Using 4:2 Compressor and CSA Adder
A1 M.B Srinivas,
A1 Himanshu Thapliyal,
A1 Vivek Reddy Kotha,
A1 Kunul Gottimukkula,
A1 Anvesh Ramasahayam,
K1 null
AB The efficiency of the Public Key encryption systems like RSA and ECC can be improved with the adoption of a faster multiplication scheme. In this paper, Modified Montgomery multiplications and circuit architectures are presented. The first modified Montgomery multiplier uses 4:2 compressor and carry save adders (CSA) to perform large word length additions. The total delay for a single modular multiplication using the proposed approach is 7XOR+1 AND gate compared to 8XOR+1AND gate of the recently proposed fastest algorithm. The second modified Montgomery multiplier uses a novel proposed hardware unit that outputs carry save representation of the 4-input operands in 3XOR delays. The total delay for a single modular multiplication using the novel hardware unit is 5XOR+1 AND gate compared to 6XOR+1AND gate of the recently proposed algorithm. The optimal transistor implementations of the proposed approaches have also been presented. The proposed transistor implementations are highly optimized in terms of area, speed and low power. The proposed Montgomery multiplication circuit will be of eminent importance when implemented for higher word length such as 1024 and 2048 as there will be saving in the propagation delays by 1024 and 2048 XOR gates respectively compared to the recently proposed fastest algorithm.
PB IEEE Computer Society, [URL:http://www.computer.org]
LA English
DO 10.1109/DELTA.2006.70
LK http://doi.ieeecomputersociety.org/10.1109/DELTA.2006.70