RT Journal Article
JF Microelectronics for Neural Networks and Fuzzy Systems, International Conference on/Microelectronics for Neural, Fuzzy, and Bio-Inspired Systems, International Conference on
YR 1996
VO 00
IS
SP 330
TI VIP: An FPGA-based Processor for Image Processing and Neural Networks
A1 Steven Pigeon,
A1 Patrice Y. Simard,
A1 Eric Cosatto,
A1 Jocelyn Cloutier,
A1 Francois R. Boyer,
K1
AB We present in this paper the architecture and implementation of the Virtual Image Processor (VIP) which is an SIMD multiprocessor build with large FPGAs. The SIMD architecture , together with a 2D torus connection topology, is well suited for image processing, pattern recognition and neural network algorithms. The VIP board can be programmed on-line at the logic level, allowing optimal hardware dedication to any given algorithm.
PB IEEE Computer Society, [URL:http://www.computer.org]
SN 1086-1947
LA English
DO 10.1109/MNNFS.1996.493811
LK http://doi.ieeecomputersociety.org/10.1109/MNNFS.1996.493811