RT Journal Article
JF 2013 Euromicro Conference on Digital System Design
YR 2007
VO 00
IS
SP 132
TI Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition
A1 Mircea Vladuþiu,
A1 Oana Boncalo,
A1 Alexandru Amaricai,
A1 Lucian Prodan,
A1 Mihai Udrescu,
K1 null
AB This paper proposes a novel approach for increasing the performance of the floating point addition, by efficiently exploiting both paths from the classical double path adder. Thus, it becomes possible to execute two floating point additions simultaneously using a single adder, each on a different path. Performing two floating point additions in this manner will requires duplication of the signs and exponent computation modules. The cost estimates show a 20% increase of the active area for the proposed adder compared with other floating point adders. In terms of performance, the latency of the proposed adder is slightly higher with respect to other double path adders. However, the increased latency is compensated by the increased throughput obtained.
PB IEEE Computer Society, [URL:http://www.computer.org]
SN
LA English
DO 10.1109/DSD.2007.54
LK http://doi.ieeecomputersociety.org/10.1109/DSD.2007.54