RT Journal Article
JF IEEE Transactions on Computers
YR 2011
VO 61
IS
SP 857
TI NoC-Based Hardware Accelerator for Breakpoint Phylogeny
A1 Ananth Kalyanaraman,
A1 Partha Pratim Pande,
A1 Souradip Sarkar,
A1 Turbo Majumder,
K1 Phylogenetics
K1 breakpoint-median problem
K1 maximum parsimony
K1 traveling salesman problem.
AB Maximum Parsimony phylogenetic tree reconstruction is based on finding the breakpoint median, given a set of species, and is represented by a bounded edge-weight graph model. This reduces the breakpoint median problem to one of solving multiple instances of the Traveling Salesman Problem (TSP), which is a classical NP-complete problem in graph theory. Exponential time algorithms that apply efficient runtime heuristics, such as branch-and-bound, to dynamically prune the search space are used to solve TSP. In this paper, we present the design and performance evaluation of a network-on-chip (NoC)-based implementation for solving TSP under the bounded edge-weight model, as used in the computation of breakpoint phylogeny. Our approach takes advantage of fine-grain parallelism from the multiple processing elements (PEs) and uses efficient NoC architecture for inter-PE communication. To accelerate the application on hardware, our PE design optimizes a particular lower bound calculation operation which typically tends to be the serial bottleneck in computation of a TSP solution. We also explore two representative NoC architectures—mesh and quad-tree—and show that the latter is more energy-efficient for this application domain. Experimental results show that this new implementation is able to achieve speedups of up to three orders of magnitude over state-of-the-art multithreaded software implementations.
PB IEEE Computer Society, [URL:http://www.computer.org]
SN 0018-9340
LA English
DO 10.1109/TC.2011.100
LK http://doi.ieeecomputersociety.org/10.1109/TC.2011.100