RT Journal Article
JF IEEE Micro
YR 2006
VO 26
IS
SP 10
TI Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance
A1 Yale N. Patt,
A1 Hyesoon Kim,
A1 Onur Mutlu,
K1 Runahead execution
K1 memory latency tolerance
K1 processors
AB Several simple techniques can make runahead execution more efficient by reducing the number of instructions executed and thereby reducing the additional energy consumption typically associated with runahead execution.
PB IEEE Computer Society, [URL:http://www.computer.org]
SN 0272-1732
LA English
DO 10.1109/MM.2006.10
LK http://doi.ieeecomputersociety.org/10.1109/MM.2006.10