RT Journal Article
JF IEEE Design & Test of Computers
YR 2007
VO 24
IS
SP 300
TI Design and CAD for Nanotechnologies
A1 Tim Cheng,
K1 CAD
K1 CMOS
K1 SEU
K1 delay testing
K1 process diagnosis
K1 redundancy
AB Recent innovations in nanoscale devices offer the potential for greater information density and system functionality. However, such devices present several new challenges. Design methodologies and tools have obtained a tremendous degree of sophistication and predictive value, and there are advantages in using the power of these tools to define a context for evaluating next-generation nanoelectronic technologies. Without a common context of systems evaluation, it will be difficult to make early viability assessments of new nanoelectronic-device approaches, nor will it be possible to strategically guide the development of these new technologies. This issue of IEEE Design & Test offers a special section on such topics. In addition, this issue presents the first in a series of tutorial articles derived from presentations at Test Technology Educational Program (TTEP) conferences. Finally, there are five general-interest articles on a wide range of topics.
PB IEEE Computer Society, [URL:http://www.computer.org]
SN 0740-7475
LA English
DO 10.1109/MDT.2007.130
LK http://doi.ieeecomputersociety.org/10.1109/MDT.2007.130