RT Journal Article
JF IEEE Transactions on Computers
YR 2005
VO 54
IS
SP 1556
TI An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors
A1 Onur Mutlu,
A1 Yale N. Patt,
A1 Hyesoon Kim,
A1 David N. Armstrong,
K1 Index Terms- Single data stream architectures
K1 speculative execution
K1 runahead execution
K1 processor performance modeling.
AB High-performance, out-of-order execution processors spend a significant portion of their execution time on the incorrect program path even though they employ aggressive branch prediction algorithms. Although memory references generated on the wrong path do not change the architectural state of the processor, they affect the arrangement of data in the memory hierarchy. This paper examines the effects of wrong-path memory references on processor performance. It is shown that these references significantly affect the IPC (Instructions Per Cycle) performance of a processor. Not modeling them leads to errors of up to 10 percent (4 percent on average) in IPC estimates for the SPEC CPU2000 integer benchmarks on an out-of-order processor and errors of up to 63 percent on a runahead-execution processor. In general, the error in the IPC increases with increasing memory latency and instruction window size. We find that wrong-path references are usually beneficial for performance because they prefetch data that will be used by later correct-path references. L2 cache pollution is found to be the most significant negative effect of wrong-path references. Code examples are shown to provide insights into how wrong-path references affect performance. We also show that it is crucial to model wrong-path references to accurately estimate the performance improvement provided by runahead execution.
PB IEEE Computer Society, [URL:http://www.computer.org]
SN 0018-9340
LA English
DO 10.1109/TC.2005.190
LK http://doi.ieeecomputersociety.org/10.1109/TC.2005.190