RT Journal Article
JF IEEE Transactions on Computers
YR 1976
VO 25
IS
SP 1132
TI Some Comments Concerning Design of Pipeline Arithmetic Arrays
A1 J.C. Majithia,
K1 Cellular arrays
K1 figure of merit
K1 parallel processes
K1 pipelining.
AB Cellular arrays for arithmetic operations usually consist of identical cells connected in an iterative or near iterative pattern. By introducing latch circuits between the rows of the array, the entire unit can be pipelined. The effect of this modification is to increase the throughput on a continuous processing basis. In most of such designs, however, the amount of hardware required for a maximally or fully pipelined array is prohibitively large. Pipeline arrays with reduced amount of intermediate latch circuits imply partially pipelined designs which of course also have a lower throughput. However, several such pipeline arrays can be operated in parallel to achieve some specified total throughput. In this correspondence this aspect is analyzed and illustrated by the design of 48-bit parallel adders.
PB IEEE Computer Society, [URL:http://www.computer.org]
SN 0018-9340
LA English
DO 10.1109/TC.1976.1674565
LK http://doi.ieeecomputersociety.org/10.1109/TC.1976.1674565